Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of a respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip packaging. Flip-chip packaging utilizes bumps to establish electrical contact between the chip's input/output (I/O) pads and the package substrate or lead frame of the package. Structurally, the bump actually contains the bump itself and an “under bump metallurgy” (UBM) located between the bump and the I/O pad.
Wafer level chip scale packaging (WLCSP) is currently widely due to low cost and relatively simple processes in comparison to other packing processes. In a typical WLCSP, post-passivation interconnect (PPI) lines such as redistribution lines (RDLs) are formed on passivation layers, followed by the formation of polymer films and bumps. An interface between the bump and the polymer layer, however, has poor adhesion and suffers moisture attack, which may induce delamination in polymer layers.